1. Field of the Invention
The present invention generally relates to a design structure for phase-locked loop circuit, and in particular a frequency adaptive level shifter circuit.
2. Description of Background
Currently, level translator circuits are used to pass signals across voltage domain boundaries. Many different level translators exist in the prior art, but many of the traditional circuit topologies are becoming unworkable as supply voltages decrease and the frequency of the signals increase.
A specific translator architecture that is not as limited by voltage headroom or signal frequency is described in the commonly assigned U.S. Pat. No. 5,491,441, entitled “Method and apparatus for generating a clock signal from a continuous oscillator signal including a translator circuit”, Ser. No. 08/269,197, issued on Feb. 13, 1996. It is understood that other means exist to establish a level translator circuit.
The intended use of the circuit described in this patent was to translate small voltage continuous signals into large full supply signals. It also functions well as a general purpose level-shifter that passes CMOS signals across a voltage domain boundary. A time constant, determined by the capacitor and resistor, are tuned for a specific frequency of application. A limitation with this is that the fixed RC product formed by a resistor and capacitor unduly limits the range of frequencies that the circuit is useful over.